/*
 * Copyright 2021 MindMotion Microelectronics Co., Ltd.
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */


#ifndef __HAL_DMA_REQUESET_H__
#define __HAL_DMA_REQUESET_H__

/* ADC. */
#define DMA_REQ_DMA1_ADC1_1       0u
#define DMA_REQ_DMA1_ADC1_2       1u

/* SPI. */
#define DMA_REQ_DMA1_SPI1_RX     1u
#define DMA_REQ_DMA1_SPI1_TX     2u
#define DMA_REQ_DMA1_SPI2_RX     3u
#define DMA_REQ_DMA1_SPI2_TX     4u

/* UART. */
#define DMA_REQ_DMA1_UART1_TX_1  1u
#define DMA_REQ_DMA1_UART1_RX_1  2u
#define DMA_REQ_DMA1_UART1_TX_2  3u
#define DMA_REQ_DMA1_UART1_RX_2  4u

#define DMA_REQ_DMA1_UART3_TX    1u
#define DMA_REQ_DMA1_UART3_RX    2u
#define DMA_REQ_DMA1_UART2_TX    3u
#define DMA_REQ_DMA1_UART2_RX    4u

/* I2C. */
#define DMA_REQ_DMA1_I2C1_TX     1u
#define DMA_REQ_DMA1_I2C1_RX     2u

/* TIM1. */
#define DMA_REQ_DMA1_TIM1_CH1    1u
#define DMA_REQ_DMA1_TIM1_CH2    2u
#define DMA_REQ_DMA1_TIM1_CH4    3u
#define DMA_REQ_DMA1_TIM1_CH3    4u

#define DMA_REQ_DMA1_TIM1_TRIG   3u
#define DMA_REQ_DMA1_TIM1_UP     4u

#define DMA_REQ_DMA1_TIM1_COM    3u
#define DMA_REQ_DMA1_TIM1_CH5    4u

/* TIM2. */
#define DMA_REQ_DMA1_TIM2_CH3    0u
#define DMA_REQ_DMA1_TIM2_UP     1u
#define DMA_REQ_DMA1_TIM2_CH2    2u
#define DMA_REQ_DMA1_TIM2_CH4    3u
#define DMA_REQ_DMA1_TIM2_CH1    4u

/* TIM3. */
#define DMA_REQ_DMA1_TIM3_CH3    1u
#define DMA_REQ_DMA1_TIM3_CH4    2u
#define DMA_REQ_DMA1_TIM3_CH1    3u

#define DMA_REQ_DMA1_TIM3_UP     2u
#define DMA_REQ_DMA1_TIM3_TRIG   3u

/* TIM16. */
#define DMA_REQ_DMA1_TIM16_CH1_1 2u
#define DMA_REQ_DMA1_TIM16_CH1_2 3u

#define DMA_REQ_DMA1_TIM16_UP_1  2u
#define DMA_REQ_DMA1_TIM16_UP_2  3u

/* TIM17. */
#define DMA_REQ_DMA1_TIM17_CH1_1 0u
#define DMA_REQ_DMA1_TIM17_CH1_2 1u

#define DMA_REQ_DMA1_TIM17_UP_1  0u
#define DMA_REQ_DMA1_TIM17_UP_2  1u


#endif /* __HAL_DMA_REQUESET_H__ */
